As is known, phase lock loops (PLLs) at least include an input reference signal, a phase comparator, an Resistive-Capacitive low pass filter, a voltage controlled oscillator (VCO), and a divider. Such PLLs produce an accurate and stable clock reference and are used in a variety of electronic circuits such as microprocessors, digital signal processors (DSPs), radio receivers, and/or radio transmitters.
A PLL produces a stable clock reference by multiplying an input reference signal, which is generated by an oscillator, to produce a desired output signal. The multiplication factor is chosen based on the frequency of the oscillator and the desired output signal. For example, if the oscillator produces a 1.2 MHz reference signal and a desired output signal has a frequency of 60 MHz, the multiplication factor is 50. The desired output signal is locked in phase and/or frequency to the input reference signal via the divider, which divides the output signal by the multiplication factor to produce a feedback signal. The feedback signal and the input reference signal are inputted to the phase comparator, which produces a pump up signal or a pump down signal. The pump up or down signal is converted by the charge pump into a current, which charges, or discharges, the capacitor. The voltage imposed on the capacitor, via the charge pump, provides the input to the VCO, which, in turn, produces the desired output signal locked in phase and/or frequency to the input reference signal.
When a PLL is in a transition phase due to initial power up or an operational change, such as a change in the multiplication factor, the output signal is inaccurate and unstable. To prevent a circuit, which incorporates the PLL, from using the output signal during the transition period, a lock indicator or lock bit is provided. The lock bit is inactivated, or low, when the PLL is in the transition period and activated, or high, when the PLL has reached an acceptable steady state condition. Acceptable steady state conditions vary depending on the circuits operating requirements, but are generally less than 10% of the desired output signal frequency.
Currently, there are several lock detection techniques. For example, one technique requires the PLL to be under damped, i.e., a damping factor less than one. With an under damped PLL, the lock detection circuit counts a predetermined number of consecutive pump-up and pump-down signals into the charge pump. By counting consecutive pump-up and down signals, it is assumed that the VCO input voltage has reached a steady state condition. While this technique provides acceptable lock indications for circuits that have a moderate range of multiplication factors, i.e., less than 256, this technique is not acceptable when the range of multiplication factors is substantially increased, i.e., to a range greater than 4000. This technique is unacceptable because of the underdamping requirement, which, for large multiplication factors, causes the damping factor to approach zero. As the damping factor approaches zero, the transition period, i.e., the time it takes the PLL to reach a steady state condition, is increased beyond acceptable level, i.e., over 100 mSec.
Another lock detector technique utilizes only the frequency of the input reference clock and the feedback divider signal. This technique involves counting a predetermined number of cycles for each signal and then comparing the signals. Having done a first count and comparison, a second count and comparison is performed. If, after both counts and comparisons, the signals match, the lock detector is activated. If the signals do not match, the lock detector is inactivated. While this technique works well in many applications, it requires a substantial amount of hardware to implement and is limited to the accuracy of the input clock.
Therefore, a need exists for a method and apparatus that overcomes the above mentioned difficulties of prior art lock detection techniques.